A 5-stage pipeline CPU implementation of MIPS instruction set architecture, including hazard detection, forwarding, flushing, and stalling, all implemented in hardware. Tested using MIPS assembly programs that I wrote, including a MIPS assembly implementation of a Fibonacci number generator. Implemented as a course project with the help of one partner over the course of a half semester.
Project link: https://git.ece.iastate.edu/ztj1/cpre-381/